Part Number Hot Search : 
5246C ATS080 5246C M5260 2SD88 HT46R2 CY8C2 MJE1300
Product Description
Full Text Search
 

To Download PEB1761 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 Preliminary
Product Brief
MetroMapperTM 2.5G
Multi-Service Framer for STS-48/ STM-16, STS-12/STM-4
The MetroMapperTM 2.5G is a multi-service framer capable of mapping datacom traffic into SONET/SDH transport payloads. On the line side, the MetroMapperTM 2.5G supports protected STS-48/STM-16 and STS-12/ STM-4 interfaces. On the client side, one OIF SPI-3 with up to 128 logical channels are provided. Data from the SPI-3 interface is encapsulated by either the GFP-F, LAPS (X.85/.86) or PPP mapping scheme. Low-order and high-order virtual concatenation (VCAT) with Link Capacity Adjustment Schemes (LCAS) for up to 128 virtual concatenated channels is supported. MetroMapperTM 2.5G provides Ethernet VLAN ID processing and enables MPLS label update processing.
Applications

Access / edge aggregation MSPP Switches and Routers
Features
Framer Multi-Rate SONET/SDH framer with STS/AU and VT/TU pointer processing capabilities Processes a single STS-48/STM-16 or a quad STS-12/STM-4, STS-3/STM-1 Payload Pointer interpretation and generation Provides full performance monitoring for high- and low-order paths Provides high-order and low-order virtual concatenation according to ITU-T G.707 Supports up to 128 virtual concatenated groups (VCG) Flexible concatenation of up to 48 high-order paths and up to 64 low-order paths into any virtual concatenation group Supports up to 1344 VT1.5/TU-11 or 1008 VT2/TU-12 low-order paths Provides following mapping schemes: - AU-4 / VC-4 / TUG-3 - AU-4 / VC-4 / TUG-3 / TUG-2 - AU-3 / VC-3 or STS-1 / STS-SPE External buffer for up to 64 ms differential delay compensation Different VCG group types are defined: - N x VC-12, N x VC-11, N x VT1.5 SPE, N x VT2 SPE (N 64) - N x VC-3, N x STS1 SPE (N 48) - N x VC-4, N x STS3c SPE (N 16) Fully integrated support for the Link Capacity Adjustment Scheme (LCAS) protocol according to ITU-T G. 7042
Supports 1+1 line protection TOH/POH add/drop interface Fully SONET/SDH compliant Encapsulation/Decapsulation Provides GFP-F mapping according to T1X1.5/ ITU-T G. 7041 PPP processing according to IETF RFC 1662 LAPS processing according to ITU-T X.85 + X.86 128 logical channels, can be independently configured PPP protocol support: MPLS Unicast & IP Version 4/6 LAPS protocol support: Ethernet and IP Version 4/6 GFP Client management frame insertion/detection SPI-3 Interface 128 logical channels running in 32 bit mode Packet mode with variable block length Interleaved channel mode Ethernet Enables Ethernet via VLAN tagging - VLAN update including tag, retag and change of VLAN IDs - performs 512-4096 entry (port, VLAN) lookup - supports VLAN double tagging Diagnostics Various loop back modes for system debugging implemented Interfaces Source synchronous STS-48/STM-16 or quad STS-12/STM-4 interfaces for working and protected links operating at 622 MHz LVDS or 78 MHz LVTTL TOH/POH add/drop interface OIF compliant SPI-3 interface Memory Interface including two DDR-SRAM and optionally 1 ZBT SRAM interface for L2 update function 66 MHz CPU interface IEEE 1149.1 JTAG boundary scan interface Documentation Data Sheet Hardware Evaluation System WINEASY Software for MS Windows with graphical user interface

w w w. i n f i n eo n . c o m / wi r e l i n e
Optical Networking
Never
stop
thinking.
Preliminary
Product Brief
Block Diagram
Memory Interface
TOH / POH ADD Interface
VLAN Processing SPI-3 MPLS label Processing
GFP-F PPP X.85/86
Data Assemb., Mapping, TU Pointer
Data Assemb., Mapping, AU Pointer
Pointer Gen.
Frame Gen.
STM16/ STS48 4x STM4/ STS12 W&P 622M / 155M
Tx System Packet
Tx Layer 2 Processing
Tx Packet Proces.
Tx LO POH VCAT LCAS
Tx HO POH VCAT LCAS
Tx POH
Tx Tx TOH TOH
Line Interface Single STM-16/ STS-48 Quad STM-4 / STS-12
Tx Line Tx Line
SPI-3 VLAN Processing MPLS label Processing Rx System Packet Rx Layer 2 Processing
GFP-F PPP X.85/86
Pointer Proc. POH Termin. Delay Calcul.
Pointer Proc. POH Termin. Delay Calcul.
DeFramer
STM16/ STS48 4x STM4/ STS12 W&P
Rx Packet Proces.
Rx LO VCAT/ LCAS
Rx HO VCAT/ LCAS
Rx Rx TOH TOH
Rx Rx Line Line
32-bit uP Interface
Memory I/F
TOH / POH DROP Interface
Product Summary
Type Sales Code Package 1020 FineLine BGA (33 x 33 mm) MetroMapperTM 2.5G PEB1761
Application Example
Ethernet/MPLS Switching Ethernet MAC QoS ; L2 VPN Service Rate Adaptation VPLS MAC VPN / PWE-3 VLAN/MPLS Processing Services GFP Mapping VCAT / LCAS Working & Protect SDH/ SONET
FE/GE
Multi-MAC Bridge
SPI-3
Ethernet/MPLS Switch
SPI-3
MetroMapper 2.5G
VCAT-LCAS Framer&Mapper
Single STM-16 / STS-48 Quad STM-4 / STS-12
TDM Switch
L2 / L3 Processing Traffic Management Switching
FE/GE Aggregation
NP / TM Switch
SPI-3
MetroMapper 2.5G
VCAT-LCAS Framer&Mapper
Single STM-16 / STS-48 Quad STM-4 / STS-12
TDM Switch
Ethernet MAC Rate Adaptation VLAN/MPLS Processing
FE /GE
Multi-MAC Bridge
SPI-3
MetroMapper 2.5G
VCAT-LCAS Framer&Mapper
Single STM-16 / STS-48 Quad STM-4 / STS-12
TDM Switch
How to reach us: http://www.infineon.com Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen (c) Infineon Technologies AG 2004. All Rights Reserved. Template: pb_tmplt.fm/4
Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office.
Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in lifesupport devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Ordering No. B115-H8436-X-X-7600 Printed in Germany PS 0604.5 R&L
Published by Infineon Technologies AG


▲Up To Search▲   

 
Price & Availability of PEB1761

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X